Thyratron shift register. Using shift registers. SHCP – clock input

1. Table of contents

2. Introduction ……………………………………………………………………………… 2

3. Review of literary sources ………………………………… 3

3.1. General information about registers………………………………… 3

3.2. General information about triggers…………………………….…... 6

3.3. Shift registers…………………………………….. 12

3.4. Universal registers…………………………………….. 20

4. Development of a shift register circuit ………………………………… 24

4.1. Initial data ……………………………………………… 24

4.2. Procedure for developing a shift register…………………..……… 24

4.3. Development of a four-phase shift register…………………… 25

5. Conclusion……………………………………………………………. 27

6. List of references …………………………………. 28

2. Introduction

Registers– the most common components of digital devices. They operate on the many related variables that make up a word. A number of operations are performed on words: receiving, issuing, storing, shifting in the bit grid, bitwise logical operations.

Shift (sequential) registers are used for shifting n-bit numbers in one direction. In addition, they can be used to shift non-numeric information.

Shift registers are used as storage devices, as converters of serial code to parallel, as delay devices and pulse counters (however, the use of shift registers as counters is quite uneconomical).

3. Review of literature sources

3.1. General information about registers

Registers consist of bit circuits that contain flip-flops and, most often, also logic elements. They act as a single unit.

According to the number of variable transmission lines, registers are divided into single-phase and paraphase, and according to the synchronization system into single-cycle, push-pull and multi-cycle. However, the main classification feature is the method of receiving and issuing data. On this basis they distinguish parallel (static) registers, sequential (shifting) And parallel-serial .

In parallel registers, words are received and output in all bits simultaneously. They store words that can be subjected to bitwise logical transformations.

In sequential registers, words are received and output digit by digit. They are called shifting, since timing signals when inputting and outputting words move them in the bit grid. A shift register can be non-reversible (with unidirectional shifts) or reversible (with the ability to shift in both directions).

Serial-parallel registers have inputs and outputs of both serial and parallel types. There are options with serial input and parallel output (SIPO, Serial Input – Parallel Output), parallel input and serial output (PISO, Parallel Input – Serial Output), as well as options with the possibility of any combination of methods for receiving and issuing words.

In parallel (static) registers, bit circuits do not communicate with each other. Common to the bits are usually clock circuits, reset/set circuits, output or receive permission, that is, control circuits. An example circuit of a static register built on D-type flip-flops with direct dynamic inputs, having reset inputs R and third-state outputs controlled by the EZ signal, is shown in Figure 1 .

Picture 1. Diagram of a static register (a) and its conventional graphic designation (b)

Modern circuit technology is characterized by the construction of registers on D-type flip-flops, mainly with dynamic control. Many have outputs with a third state. Some registers are classified as buffer registers, that is, they are designed to work with large capacitive and/or low-resistance active loads. This ensures their operation directly on the highway (without additional interface circuits).

Static registers are used to create blocks of register memory—register files.

Main functions of registers:

1) Data storage,

2) Reception of information,

3) Issuing information,

4) Information shift,

5) Code conversion,

6) Setting the desired number to zero or one,

7) Bitwise logical operations: disjunction, conjunction, addition modulo 2.

3.2. Understanding Triggers

Triggers – big class electrical devices, allowing it to remain in one of two (or more) stable states for a long time and alternate them under the influence of external signals (as a result of the regenerative process (transition process in electrical circuit, covered by the PIC)).

A trigger is a pulse logical device with memory (memory element – latch).

There are more than a dozen different integral triggers. Their classification is based on:

Functional sign

A method for writing information to a trigger.

Based on their functional characteristics, there are T-triggers, JK-triggers, RS-triggers, D-triggers, combined triggers (TV, DV, E, R), etc.

Based on the method of recording (receiving) information, they are distinguished:

8) Asynchronous triggers:

a) with internal delay;

b) controlled by the input pulse level;

9) Synchronous triggers (clocked):

a) with internal delay;

b) controlled by the level of the timing pulse:

Single-cycle action (single-stage);

Multiple action.

Information is written to clocked triggers only when an enabling clock pulse is applied. Such triggers are divided into level-controlled (a certain signal level is required for operation) and edge-controlled (do not depend on the signal level, its presence is important) of the timing pulse. Clock pulses are sometimes also called synchronizing, executive, or command signals (usually denoted in diagrams by the letter C - Clock).

Dynamic input can be direct or inverse. Direct dynamic control allows switching when the clock signal changes from zero to one (). Inverse dynamic control - changing the clock signal from one to zero ().

Timing pulse edge control:

Timing pulse decay control:

Control of the upper level of the timing pulse:

Control of the lower level of the timing pulse:

Clocked triggers with an internal delay (triggered when the signal ends) are, as a rule, single-ended. Multi-cycle triggers fire after n-nogo impulse.

The RS trigger has two information inputs: S (Set) and R (Reset). Simultaneous application of S and R signals is not allowed. On Figure 2 shows a synchronous RS trigger triggered by the edge of the timing signal.

Figure 2. Synchronous RS trigger

In addition to inputs, the simplest RS trigger also has two outputs. Outputs indicate Q And . Exit Q called direct, a - inverse. The voltage levels at both outputs are mutually inverse: if the signal Q= 1, then = 0, or if Q= 0, then = 1. It should also be noted that the state of the trigger in which Q= 1, a = 0, is called unit. When the trigger is zero Q= 0 and = 1. When signals arrive at the inputs of the trigger, depending on its state, either switching occurs or the original state is preserved.

Figure 3. - trigger: its conventional graphic designation and a circuit with two logical elements AND-NOT

On Figure 3 the simplest trigger is shown - type . Only two NAND gates are used here. Purpose of the inputs: - to set the trigger to a single state and - to return to the zero state. The dashes above the input designations indicate that the flip-flop switches when a high-level input voltage is replaced by a low-level voltage ( figure 4). It is easy to see that when no signals are received at the inputs, the flip-flop retains its state. If, for example, Q= 1 and = 0, that is, the trigger is in a single state, then since the output of DD1 is connected to one of the inputs of DD2, and the output of DD2 is connected to one of the inputs of DD1, voltage is applied to the two inputs of DD2

Figure 4. Operation timing diagram - trigger

high, and at the output - low (= 0) level. At the same time, at one of the inputs of DD1 the voltage is low, and at the output it is high. If a signal with the indicated polarity now arrives at the input (moment t1 , figure 4), the state of the trigger will not change, because the arrival of a signal at the second input DD1 will temporarily change only the combination of signals at the inputs (before the signal was sent it was 1 and 0, but it became 0 and 0), but the output state of DD1 remains unchanged. If, however, a signal arrives at the input (moment t2), both inputs of DD2 will already have voltages of different levels, the state logic elements will change and its output will have a high level voltage. Both inputs of DD1 will have high-level voltages, and low voltages at the output, that is, the trigger will “overturn” and go into another state: Q= 0 and = 1.

From the above it follows that a change in the state of the trigger occurs only when low-level signals alternate at the inputs and . Moreover, if such signals arrive at both inputs simultaneously, then after their termination the state of the trigger will become undefined (state Q= 0 or Q= 1 equally likely). Therefore, simultaneous low-level signals are not allowed on both inputs.

The operation of a trigger is characterized by a table of states (indices n And n+1 indicate that the signal belongs to a moment in time tn and the next one after him tn+1):





		Uncertain state

Simultaneous supply of low level voltage to both inputs of the trigger is not allowed.

An RS type trigger, like a flip-flop, “remembers” which of the two inputs (R or S) received the last signal: if the input is R, the trigger is in the zero state ( Q= 0 and = 1), and if the input is S, then in a single state ( Q= 1 and = 0).

Figure 5. R.S. - trigger: its conventional graphic designation and circuit with four logical elements AND-NOT

On Figure 5 shows a diagram of an RS flip-flop made on NAND logic elements. It differs from the flip-flop circuit in that an inverter (DD3 and DD4) is added to each input, which only provide the required level of input signals.

Changing input signals from low to high leads to a change in the state of the trigger (moments t1, t2, t2 and t5; in the moment t4 no rollover occurs, since the trigger was already set to the single state at the previous moment - t3, Figure 6).

Figure 6. Timing diagram of RS operation - trigger

Everything said regarding the RS trigger also applies to the -trigger. The only difference concerns the inversion of the input signal levels (R instead of and S instead of ).

The operation of the RS flip-flop is characterized by the following state table:





		Uncertain state

3.3. Shift registers

Trigger shift register call a set of triggers with certain connections between them, in which they act as a single device. Sequential (shift) registers are a chain of bit circuits connected by carry circuits.

In single-cycle registers shifted one bit to the right ( Figure 7) the word is shifted when a synchronization signal arrives. Input and output are serial (DSR – Data Serial Right). On Figure 8 shows a left-shifted register circuit (DSL data input - Data Serial Left), and Figure 9 illustrates the principle of constructing a reversible register, in which there are connections between flip-flops with both adjacent bits, but the corresponding signals allow the operation of only one of these connections (commands “left” and “right” are not given simultaneously).

Figure 7. Right-shift register circuit

Drawing 8 . Left shift register circuit

Drawing 9 . Reversing register circuit

According to synchronization requirements, in shift registers that do not have logical elements in inter-bit connections, one-stage level-controlled flip-flops cannot be used, since some flip-flops can switch repeatedly during the action of the enabling level of the clock signal, which is unacceptable. In these schemes, triggers with dynamic control (two-stage) should be used.

The appearance of logical elements and, moreover, logical circuits of non-unit depth in inter-bit connections simplifies the fulfillment of the operating conditions of registers and expands the range of types of flip-flops suitable for these circuits.

Multi-cycle shift registers are controlled by several clock sequences. Of these, the most famous are push-pull ones with main and additional registers, built on simple single-stage triggers controlled by a level. At clock C1, the contents of the main register are rewritten into the additional register, and at clock C2 they return to the main register, but to adjacent bits, which corresponds to a word shift. In terms of equipment costs and performance, this option is close to a single-cycle register with two-stage flip-flops.

The shift register contains a set of flip-flops with certain connections between them, and the organization of these connections is such that when a clock pulse is applied, common to all flip-flops, the output state of each flip-flop is shifted to the neighboring one. Depending on the organization of connections, this shift can occur to the left or to the right:

Shift left

Shift right

Entering information into the register can be done different ways, however, parallel or serial input is most often used, in which a binary number is entered either simultaneously into all bits of the register, or sequentially over time in individual bits. In pulse counters, shift registers with sequential input and output of information and with a shift to the right are used. On Figure 10 a The diagram of a four-bit shift register made on RS flip-flops is shown. In this scheme, each output Q The trigger is connected to the S input of the subsequent discharge, and each output is connected to the R input. The clock inputs of all flip-flops are connected together, and the synchronization signal is received by one common pulse through the AND-NOT logical element (DD7). The state of the first trigger is determined by the input signals at the inputs X1, X2 of the AND-NOT logical element (DD5). Current information is supplied to input X1, and a signal to allow its transmission to input X2. The NOT gate (DD6) is used to invert the input signal applied to the S input.

On Figure 10 b The timing diagrams of the output signals of flip-flops and the state of registers when writing a single signal to the first digit are shown. If, upon arrival of the first clock pulse, the signals X1 = X2 = 1 are set at the inputs X1 and X2, which are then removed by the arrival of the second clock pulse, then as a result the signal will be written to the first trigger Q 1 = 1. With the arrival of the second clock pulse, a signal will be written to the first trigger Q 1 = 0, and a signal will appear at the output of the second trigger Q 2 = 1, which was previously at the output of the second trigger. When subsequent clock pulses arrive, a single signal is moved sequentially to the third and fourth flip-flops, after which all flip-flops are set to the zero state.

n	*Q 1*	*Q 2*	*Q 3*	*Q 4*

Drawing 10 . Diagram of a four-phase shift register (a), timing diagrams of its signals and register states when writing a single signal to the first digit (b)

Shift registers can also be implemented using D flip-flops or JK flip-flops. All shift registers have the following provisions:

1) it is necessary to pre-set the initial state and enter a unit into the first trigger

2) for register from n triggers after admission n input clock pulses, the initially entered unit is output, as a result of which the direct outputs of all registers are in the zero state.

Integrated shift register chips are reversible, that is, they perform a shift in any direction: left or right. The direction of the shift is determined by the value of the control signal.

Figure 11. Implementation of a shift register on single-ended RS flip-flops

The serial shift register has two disadvantages: it allows only one bit of information to be entered on each clock pulse, and, in addition, each time the information in the register is shifted to the right, the rightmost information bit is lost. On Figure 12 shows a system that allows simultaneous parallel loading of 4 bits of information.

Figure 12. Structural scheme 4-bit parallel register

Inputs 1, 2, 3, 4 in this device are information inputs. This system can be equipped with another useful characteristic - the possibility of circular movement of information, when data from the output of the device is returned to its input and is not lost.

Figure 13. Logic circuit of a four-bit parallel ring register

The circuit of a 4-bit parallel ring shift register is shown in Figure 13. This shift register uses four JK flip-flops. Thanks to the chain feedback the information entered into the register, which is usually lost at the output of the fourth flip-flop, will circulate through the shift register. The signal to clear the register (set its outputs to state 0000) is the logical level 0 at the CLR input. Parallel data load inputs 1, 2, 3 and 4 are connected to trigger preset (PS) inputs, allowing logic 1 to be set on any output (1, 2, 3, 4). If a logical 0 is applied to one of these inputs even briefly, then a logical 1 will be set at the corresponding output. Applying clock pulses to the C inputs of all JK flip-flops leads to a shift of information in the register to the right. From the fourth trigger, data is transferred to the first trigger (circular movement of information).

Table 1.

№ lines	Inputs		Exits
		Clock No.
		Clock No.

The operating principle of a parallel shift register is described in table 1. When the power is turned on, any binary combination can be set at the register outputs, such as, for example, in line 1 of the table. Applying a logic 0 to the inputs of the CLR flip-flops initiates clearing the register (line 2). Next (line 3) the binary combination 0100 is loaded into the register. Consecutive clock pulses cause the entered information to shift to the right (lines 4 - 8). In lines 5 and 6: the one from the rightmost flip-flop (the fourth) is transferred to the left-most flip-flop (the first). In this case, we can talk about the circular movement of a unit in the register. Next (line 9), clearing the register is again initiated using the CLR input. The new binary combination 0110 is loaded (line 10). Applying 5 clock pulses (lines 11-15) results in a circular shift of information 5 positions to the right. It takes 4 clock pulses to return the data to its original state.

If the shift register is by Figure 13 break the feedback loop, then we get a regular parallel shift register: the possibility of circular movement of information will be excluded.

Figure 14. Three-cycle shift register on RS flip-flops

3.4. Universal Registers

Often, instead of conventional serial or parallel ones, it is necessary to use more complex shift registers: with parallel synchronous recording of information, reversible, reversible with parallel synchronous recording. Such registers are called universal .

There are many series of IC registers, multi-mode (multi-function) or universal, capable of performing a set of micro-operations. Multi-mode is achieved by composing in the same scheme the parts necessary to perform various operations. Control signals that specify the type of work performed in given time operations activate the parts of the circuit necessary for this.

Figure 15. Universal shift registers: a – K155IR13, b – K500IR141, c – KM155IR1

On Figure 15 three typical representatives of universal shift registers of the K155, KM155 and K500 series are shown.

Chip IR13 ( Figure 15 a) is an eight-bit reversible shift register with a permissible clock frequency of up to 25 MHz and a current consumption of up to 40 mA. It has parallel inputs and outputs, an asynchronous reset input, DSL (left shift) and DSR (right shift) inputs based on the clock pulse differential C, mode selection inputs S0 and S1. When S0 = 0, S1 = 1, information is shifted to the right, when S0 = 1, S1 = 0 – to the left, and when S0 = S1 = 1 – information is written to the register.

Chip IR141 ( Figure 15 b) is a universal four-bit shift register built on emitter-coupled logic. Clock frequency– up to 150 MHz. Current consumption is at least 120 mA. When S0 = 0, S1 = 1, the information is shifted to the right, when S0 = 1, S1 = 0 – to the left, and when S0 = S1 = 1 – storing the number, when S0 = S1 = 0 – setting the number.

IR1 microcircuit ( Figure 15 in) is a shift register with synchronous recording of information on RS flip-flops. Inputs 1 – 4 are intended for parallel recording of information, input D is for sequential recording. Input V – control. When V = 0, the circuit operates as a shift register based on the negative edge (from 1 to 0) of the C1 signal, and when V = 1, the circuit operates in the mode of synchronous writing to the register of input signals 1 – 4 based on the negative edge of the C2 signal.

Registers having different types of input and output serve as the main blocks of converters of parallel codes into serial ones and vice versa. On Figure 16 shows a circuit of a parallel-to-serial code converter based on an eight-bit register of the SI/PO/SO type. In this circuit, a negative starting pulse St, which sets the level of logical zero at the upper input of element 1, creates a single parallel data reception signal at input L (Load), through which the converted word is loaded into bits 1–7 of the register, and into bit zero – constant 0. A constant 1 is applied to the serial input of the DSR. Thus, after loading, a word is formed in the register. Clock pulses arriving at input C cause the word to shift to the right. Shifts output the word in serial form through the output of Q7. Following the information bits there is a 0, followed by a chain of ones. While zero is not removed from the register, a single signal operates at the output of element 2. After zero is output, all inputs of element 2 become single, its output becomes zero and generates a signal through element 1 automatic download next word, after which the conversion cycle is repeated.

Figure 16. Parallel to serial converter circuit

Modern registers are poorly suited for performing bitwise logical operations, but if necessary, they can be performed using registers on RS flip-flops. To perform the OR operation, the first word is supplied to the S input of the static register with the initial zero state, the unit digits of which set the corresponding flip-flops. Then, without resetting the register, the second word is supplied to the S outputs.

When performing a bitwise operation AND in the first clock cycle, the first word is supplied to the S inputs of the register, establishing those bits of the register in which this word has ones. Then the second word should be applied to the register. In order for the register to retain units only in those bits in which both words have units, the second word is supplied to the inputs of R flip-flops in inverse form.

Addition modulo 2 can be performed by a circuit with T-type flip-flops in the bits by applying two words to it sequentially in time.

4. Design of a shift register circuit

4.1. Initial data

The clock pulses are set to positive polarity.

4.2. Shift Register Design Procedure

a) Consideration of general register design requirements.

b) Development of a shift register.

c) Description of the operation of the developed circuit.

4.3. Development of a four-phase shift register

It is necessary to develop a four-phase shift register using RS flip-flops. Let it be right-shifting. To do this, we need four synchronous RS flip-flops with clock pulse edge synchronization and a certain number of logic elements to create transfer circuits. Since shift registers with serial input and output have low performance, we will develop a circuit with parallel input and output.

Figure 17. Developed circuit of a right-shifting synchronous register on RS flip-flops

By inverting the signal at the trigger inputs, we ensure that supplying voltages of the same levels to the S and R inputs is impossible. This means that when S = 0, R = 1, we get 0 at the output, when S = 1, R = 0, we get 1 at the output. At the inputs of the shift register, it is necessary to install four elements with the following truth table:

By connecting the fourth output to the first input, we get a ring right-shifting register. Information from output Q4 will not be lost, but will be recirculated.

Since such a shift register is four-bit, the number of possible combinations at the input will be 16. Let's consider the operation of our register when some combinations are supplied to the input.

Combination No.	Entrance		Exit
Combination No.		Clock No.

5. Conclusion

The course project examined the classification of registers and the principles of their operation. The types and principles of operation of triggers as the main components of registers are considered. Shift registers and, in particular, shift registers on RS flip-flops were examined in detail.

A right-shifting ring synchronous four-bit register based on four RS flip-flops and eight logic elements was also designed. A table is provided that describes the operation of the register for some input combinations.

6. List of references used

1. Pryanishnikov V.A. Electronics (course of lectures). – S-P., 1998

2. Skarzhepa V.A., Lutsenko A.N. Electronics and microcircuitry (part one). – K.: Higher School, 1989

3. Budishchev M.S. Electrical engineering, electronics and microprocessor technology. – L.: Poster, 2001

4. Ugryumov E.P. Digital circuitry. – S-P., 2000

5. Directory of modern integrated circuits

A flip-flop shift register is a set of flip-flops with certain connections between them, in which they act as a single device. Sequential (shift) registers are a chain of bit circuits connected by carry circuits.

In single-cycle registers with a one-bit shift to the right (Figure 7), the word is shifted when a synchronization signal is received. Input and output are serial (DSR - Data Serial Right). Figure 8 shows the circuit of a register with a shift to the left (DSL data input - Data Serial Left), and Figure 9 illustrates the principle of constructing a reverse register, in which there are connections between flip-flops with both adjacent bits, but the corresponding signals only allow the operation of one of these connections (commands “left” and “right” are not given simultaneously).

Figure 7. Right-shift register circuit

Figure 8. Left-shift register circuit

Figure 9. Reversing register circuit

Shift left

Shift right

Entering information into a register can be done in various ways, but most often parallel or sequential input is used, in which a binary number is entered either simultaneously into all bits of the register, or sequentially over time in individual bits. In pulse counters, shift registers with sequential input and output of information and with a shift to the right are used. Figure 10 a shows a diagram of a four-bit shift register made on RS flip-flops. In this circuit, each Q output of the flip-flop is connected to the S input of the subsequent digit, and each output is connected to the R input. The clock inputs of all flip-flops are connected together, and the synchronization signal is received by one common pulse through the NAND gate (DD7). The state of the first trigger is determined by the input signals at the inputs X1, X2 of the AND-NOT logical element (DD5). Current information is supplied to input X1, and a signal to allow its transmission to input X2. The NOT gate (DD6) is used to invert the input signal applied to the S input.

Figure 10 b shows the timing diagrams of the output signals of the triggers and the state of the registers when writing a single signal to the first digit. If, upon arrival of the first clock pulse, the signals X1 = X2 = 1 are set at the inputs X1 and X2, which are then removed by the arrival of the second clock pulse, then as a result, the signal Q1 = 1 will be written to the first trigger. With the arrival of the second clock pulse, the first trigger will the signal Q1 = 0 is recorded, and the signal Q2 = 1 appears at the output of the second trigger, which was previously at the output of the second trigger. When subsequent clock pulses arrive, a single signal is moved sequentially to the third and fourth flip-flops, after which all flip-flops are set to the zero state.

Figure 10. Schematic of a four-phase shift register, timing diagrams of its signals and register states when writing a single signal to the first digit

Shift registers can also be implemented using D flip-flops or JK flip-flops. All shift registers have the following provisions:

1) it is necessary to pre-set the initial state and enter a unit into the first trigger
2) for a register of n flip-flops, after the arrival of n input clock pulses, the initially entered unit is output, as a result of which the direct outputs of all registers are in the zero state.

Integrated shift register chips are reversible, that is, they perform a shift in any direction: left or right. The direction of the shift is determined by the value of the control signal.

Figure 11. Implementation of a shift register on single-ended RS flip-flops

The serial shift register has two disadvantages: it allows only one bit of information to be entered on each clock pulse, and, in addition, each time the information in the register is shifted to the right, the rightmost information bit is lost. Figure 12 shows a system that allows simultaneous parallel loading of 4 bits of information.

Figure 12. Block diagram of a 4-bit parallel register

Figure 13. Logic diagram of a four-bit parallel ring register

The circuit of a 4-bit parallel ring shift register is shown in Figure 13. Four JK flip-flops are used in this shift register. Thanks to the feedback loop, the information entered into the register, which is usually lost at the output of the fourth flip-flop, will circulate through the shift register. The signal to clear the register (set its outputs to state 0000) is the logical level 0 at the CLR input. Parallel data load inputs 1, 2, 3 and 4 are connected to trigger preset (PS) inputs, allowing logic 1 to be set on any output (1, 2, 3, 4). If a logical 0 is applied to one of these inputs even briefly, then a logical 1 will be set at the corresponding output. Applying clock pulses to the C inputs of all JK flip-flops leads to a shift of information in the register to the right. From the fourth trigger, data is transferred to the first trigger (circular movement of information).

Line no.
		Clock No.

The operating principle of a parallel shift register is described in Table 1. When the power is turned on, any binary combination can be set at the register outputs, such as, for example, in row 1 of the table. Applying a logic 0 to the inputs of the CLR flip-flops initiates clearing the register (line 2). Next (line 3) the binary combination 0100 is loaded into the register. Consecutive clock pulses cause the entered information to shift to the right (lines 4 - 8). In lines 5 and 6: the one from the rightmost flip-flop (the fourth) is transferred to the left-most flip-flop (the first). In this case, we can talk about the circular movement of a unit in the register. Next (line 9), clearing the register is again initiated using the CLR input. The new binary combination 0110 is loaded (line 10). Applying 5 clock pulses (lines 11-15) results in a circular shift of information 5 positions to the right. It takes 4 clock pulses to return the data to its original state.

If we break the feedback loop in the shift register in Figure 13, we will get a regular parallel shift register: the possibility of circular movement of information will be excluded.

Figure 14. Three-cycle shift register on RS flip-flops

1. Table of contents

2. Introduction ……………………………………………………………………………… 2

3. Review of literary sources ………………………………… 3

3.1. General information about registers ………………………………… 3

3.2. General information about triggers…………………………….…... 6

3.3. Shift registers…………………………………….. 12

3.4. Universal registers…………………………………….. 20

4. Development of a shift register circuit ………………………………… 24

4.1. Initial data ……………………………………………… 24

4.2. Procedure for developing a shift register…………………..……… 24

4.3. Development of a four-phase shift register…………………… 25

5. Conclusion……………………………………………………………. 27

6. List of references …………………………………. 28

2. Introduction

Shift (sequential) registers are used for shifting n-bit numbers in one direction. In addition, they can be used to shift non-numeric information.

Shift registers are used as storage devices, as converters of serial code to parallel, as delay devices and pulse counters (however, the use of shift registers as counters is quite uneconomical).

3. Review of literature sources

3.1. General information about registers

Registers consist of bit circuits that contain flip-flops and, most often, also logic elements. They act as a single unit.

In parallel registers, words are received and output in all bits simultaneously. They store words that can be subjected to bitwise logical transformations.

Picture 1. Diagram of a static register (a) and its conventional graphic designation (b)

Static registers are used to create blocks of register memory—register files.

Main functions of registers:

1) Information storage,

2) Reception of information,

3) Providing information,

4) Information shift,

5) Code conversion,

6) Setting the desired number to zero or one,

7) Bitwise logical operations: disjunction, conjunction, addition modulo 2.

3.2. Understanding Triggers

Triggers – a large class of electrical devices that allow it to remain in one of two (or more) stable states for a long time and alternate them under the influence of external signals (as a result of the regenerative process (transient process in an electrical circuit covered by a PIC)).

A trigger is a pulse logical device with memory (memory element – latch).

There are more than a dozen different integral triggers. Their classification is based on:

Functional sign

A method for writing information to a trigger.

Based on their functional characteristics, there are T-triggers, JK-triggers, RS-triggers, D-triggers, combined triggers (TV, DV, E, R), etc.

Based on the method of recording (receiving) information, they are distinguished:

8) Asynchronous triggers:

a) with internal delay;

b) controlled by the input pulse level;

9) Synchronous triggers (clocked):

a) with internal delay;

b) controlled by the level of the timing pulse:

Single-cycle action (single-stage);

Multiple action.

Control of the edge of the timing pulse: Control of the fall of the timing pulse: Control of the upper level of the timing pulse:

Control of the lower level of the timing pulse:

Clocked triggers with an internal delay (triggered when the signal ends) are, as a rule, single-ended. Multi-cycle triggers fire after n-nogo impulse.

Figure 2. Synchronous RS trigger

In addition to inputs, the simplest RS trigger also has two outputs. Outputs indicate Q And

. Exit Q called direct, a - inverse. The voltage levels at both outputs are mutually inverse: if the signal Q= 1, then = 0, or if Q= 0, then = 1. It should also be noted that the state of the trigger in which Q= 1, a = 0, is called unit. When the trigger is zero Q= 0 and = 1. When signals arrive at the inputs of the trigger, depending on its state, either switching occurs or the original state is preserved.

Figure 3. - trigger: its conventional graphic designation and a circuit with two logical elements AND-NOT

Shift registers are widely used to store and process information in microcomputers. A shift register consists of a series of flip-flops (one for each bit of information) connected so that the output of each flip-flop is connected to the input of the next one. The information in the register is shifted one bit to the right or left with each clock pulse. This device is ideal for processing serial information (supplied one bit at a time), converting parallel information (all bits arriving simultaneously) into serial and serial into parallel.

Shift registers are implemented on SIS devices made using RS, JK, or D flip-flops, and the differences between them are mainly related to the method of processing input and output data. This section describes the main types of these registers.

Rice. 2.29. Typical 4-bit register with serial input.

Rice. 2.30. Timing diagram of the operation of a 4-bit shift register.

Serial input shift register.

A serial input shift register is a device in which data is input sequentially, as shown in Fig. 2.29 for a 4-bit shift register. In this case, D-triggers are used. The register works as follows. In the initial position, a reset pulse (logical 0) is applied to the “Set to 0” input, setting outputs Q 0 -Q 3 to 0. Then the first bit of data is supplied to the serial input. When exposed to the rising edge of the first clock pulse, Q 0 takes on a value equal to D 1 . Then D 2 is supplied to the serial input. When exposed to the leading edge of the second clock pulse, Q 0 =D 2 and Q 1 =D 1 . This process continues, after four clock pulses we have Q 0 =D 4, Q 1 =D 3, Q 2 =D 3, Q 3 =D 1. The timing diagram for sequentially arriving input data is shown in Fig. 2.30.

The data output can be either serial or parallel. In the latter case, the shift register operates as a serial-to-parallel converter. Obviously, for shift registers that have a large number of bits (more than eight), parallel outputs are not practical due to the large number of outputs in the IC package. There are shift registers with more than 1000 bits.

Parallel input shift register

A shift register with a parallel input is a device in which input data arrives simultaneously through parallel information channels (Fig. 2.31). Data is written to the register as follows. First, the contents of the register are reset by applying a pulse (logical 0) to the “Set to 0” input. Next, D 1 -D 4 are supplied to the inputs and a pulse (logical 1) is supplied to the recording input. This causes information to be written to all registers using the preset inputs. After that, with each clock pulse, the information is shifted one bit to the right. Data output can be either serial or parallel. Many IC-based shift registers have parallel input and serial output. These devices are known as parallel-to-serial converters.

In the shift registers described above, the shift was made in one direction at each clock pulse. In many cases, however, it is desirable to be able to shift information both left and right. Registers that have this ability are called reversible shift registers. Shift control in such registers is carried out by connecting the outputs of flip-flops to the corresponding inputs when shifting left or right. The shift direction is controlled by the "Operating method" input. Reversible shift registers with serial and parallel inputs and outputs are called universal shift registers.

Rice. 2.31. Typical 4-bit shift register with parallel output.

Register example

In the IR1 microcircuit, each bit is formed by a synchronous two-stage RS trigger with input logic (Fig. 2.32). The shift register allows you to implement the following operating modes: recording information using parallel code; shift right; shift left. The register operating mode is controlled via inputs VI, V2, C1, C2 (pins 1, 6, 9, 8).

Rice. 2.32. Logical structure IR1 microcircuits

To write to the information register using a parallel code, apply a high level voltage to the V2 mode control input, a low level voltage to the C2 input, and information signals to the D1 - D8 inputs. The voltage at inputs C1, VI can be any. To shift the information recorded in the parallel code to the right, clock pulses are applied to input C2 (pin 8). In this case, the voltage at the V2 input (pin 6) should be maintained at a high level. When performing operations with data presented in a serial code, input information in the form of a sequence of pulses is supplied to the information input VI (pin 1), clock pulses to the synchronization input C1 (pin 9), and a low level voltage is maintained at inputs V2, D1 - D8. The operating modes of the IS IR1 for various types of information recording are presented in Table. 2.11.

When shifting to the left, a high level voltage is applied to the mode selection input V2, which blocks the passage of clock pulses for shifting to the right. If, in this case, the parallel code of a number is not supplied to the inputs of the parallel code of bits D1 - D8, but the output of the last bit is connected to the input of the parallel code of the previous bit, its output with a similar input of the previous bit, etc., then we get a left shift register. The input of the serial code in this case is the input of the parallel code of the last bit of the shift register.

IR1 microcircuits can be used as the main element in arithmetic buffer memory devices, a delay element for n clock cycles, a converter of serial codes to parallel and vice versa, a frequency divider, a looped pulse distributor, etc.

Register. Shift register

A register is a device made of flip-flops to perform a series of actions with binary numbers. For those who do not know what a trigger is, we recommend that you get acquainted with the simplest RS trigger.

The simplest function of registers is to remember a number and store it for a long time. These devices are called storage registers. Here's a simple example.

The number that needs to be saved is supplied to inputs D0 - D2. As soon as a synchronization pulse appears at input C, the number is written to the trigger, changing their state. The figure shows a three-bit holding register. When the number 111 2 is supplied to the inputs, it will also appear on the direct outputs of the triggers ( Q0 - Q2). At inverse outputs ( Q0 - Q2) will naturally be 000 2 . Signal R ( Reset) or reset, the flip-flops are set to the zero state.

Typically registers consisting of 4, 8, or 16 flip-flops are used. Image of a four-bit register on circuit diagrams may be like this.

The figure does not show the inverse outputs of the triggers and the R signal. Registers are always designated by Latin letters RG. If the register is shifting, then an arrow directed to the left, right or double is drawn under the designation.

Shift registers or shift registers.

A shift register is a device consisting of several flip-flops connected in series, the number of which determines the register's capacity. Registers are widely used in computer technology to convert codes. Parallel to serial and vice versa.

In addition, shift registers are the basis ( ALU) of an arithmetic-logical device, since when a binary number written in a register is shifted one digit to the left, the number is multiplied by two, and when a number is shifted one digit to the right, the number is divided by two. Therefore, the most widespread reversible or bidirectional registers.

Consider a four-bit shift register that converts serial binary code into parallel binary code. The use of serial code is justified by the fact that huge amounts of information can be transmitted over one line. An example of this would be the Universal Serial Bus - USB port any device. The number of triggers in this register can be any. It is enough to connect the direct output Q3 With D input of the next trigger and so on until the required capacity is reached.

The register works as follows. The first information bit arrives at the input D0. Simultaneously with this bit, a clock pulse arrives at the input WITH. Inputs WITH all triggers included in the register are combined with each other. With the arrival of the first clock pulse, the level at the input D0 written to the first trigger and from the output Q0 comes to the input of the next trigger, but writing to the second trigger does not occur, since the clock pulse has already ended.

When the next clock pulse arrives, the level present at the input of the second flip-flop is stored in it and goes to the input of the third flip-flop. At the same time, the next information bit is stored in the first flip-flop. After the arrival of the fourth clock pulse, the logical levels that were sequentially received at the input will be recorded in the four flip-flops of the register D0.

Let's say these are levels 0110 2. Then this binary number can be displayed by connecting LEDs to the trigger outputs. This is how the considered register is depicted on a schematic diagram.

It can be seen that there is an arrow on the conventional image - an indicator that this is a shift register.

Let's look at how a four-bit universal shift register works. K155IR1(analogue - SN7495N). Here is its internal structure.

The register contains four D-flip-flops, which are interconnected using additional AND - OR logic elements, which allow the implementation of various functions. On the diagram:

V2 - control input. It is used to select the operating mode of the register.

Q1 - Q4 outputs of triggers from which the parallel code is removed.

V1 - input for supplying serial code.

C1, C2 - clock pulses.

D1 - D4 - inputs for writing parallel code.

The register operation algorithm is as follows. If a low potential is applied to input V2, clock pulses are applied to C1, and information bits are applied to input V1, then the register shifts to the right. After receiving four bits at the outputs of flip-flops Q1 - Q4, we obtain a parallel code. In this way, the serial code is converted into parallel.

For reverse conversion, the parallel code is written to inputs D1 - D4, applying a high potential to input V2 and clock pulses to input C2. Then, by applying a low potential to input V2 and clock pulses to input C1, we shift the recorded code, and the serial code is removed from the output of the last trigger.

In terms of its structure, this is one of the simplest shift registers.

Shift registers in digital technology can serve as the basis on which assemblies with interesting properties are assembled. These are, for example, ring counters, which are called Johnson counters. Such a counter has a number of states twice as large as the number of its constituent flip-flops. For example, if a ring counter consists of three flip-flops, then it will have six stable states. Nothing is supplied to the counter input except clock pulses. In the initial state, all flip-flops are “reset”, that is, there are logical zeros at the direct outputs of the triggers, but at the input D the first trigger from the inverse output of the third trigger is a logical unit. Let's start sending clock pulses and the process begins.

The truth table clearly shows how the binary code changes when six clock pulses arrive.

N	Q 2	Q 1	Q 0
1	0	0	1
2	0	1	1
3	1	1	1
4	1	1	0
5	1	0	0
6	0	0	0

Now you know what a register is and how it can be used in practice. The basis of any register is a trigger. The number of flip-flops in a register determines its capacity. Those who are interested in microcontrollers know that the most important element of any microcontroller, be it PIC, AVR, STM or MSP, is the register.