Overview of printed circuit board design technologies Cadence Allegro PCB Designer

Anatoly Sergeev,
specialist at Orkada for Cadence Design Systems, Inc. products, author of numerous articles. Graduated from Vladimir State University with a degree in “Design and technology of radio-electronic equipment”

The development of electronics is driven by the increasing performance and functionality of semiconductor technologies. New devices are becoming increasingly complex, and component pin configurations, pitch, and packaging density are important design considerations. Also, new devices use modern interfaces: DDR3, DDR4, PCI Express Gen3, USB 3.0 and others, which require new types of implementation on the printed circuit board. All this leads to an ever-increasing demand for new packaging methods that increase the density of interconnects on a printed circuit board. Today, to solve such complex problems, engineers need modern technologies for designing systems at the printed circuit board level that will meet technological and methodological requirements. These include, for example, the Cadence Allegro PCB Designer software package, some of the most important functions of which are described in this publication.

Connection planning and routing

Complex circuit boards with many electrical and process constraints, high component density, and multiple high-speed signal data buses require a new design approach. The use of traditional and outdated CAD systems, such as P-CAD, becomes unacceptable, since they are not able to ensure the readiness of such projects in the shortest possible time. CAD systems are coming to the fore, which are actively developing and meet modern realities in the electronics industry. Cadence Allegro PCB Designer, combined with the Interconnect Flow Planner option, provides a unique feature for creating an interconnect plan and then converting it into a finished routing. This planning and routing mechanism gives the engineer the opportunity to lay large arrays of signals in the form of special objects - signal harnesses, which can significantly simplify the design and radically reduce development time (Fig. 1).

The engineer sees on the screen not hundreds or thousands of intersecting electrical lines, but a plan for laying large arrays of these connections. It is clear that this approach greatly increases the efficiency of work - it is possible to lay signal harnesses between layers, plan the placement of vias, avoid crossing bundles with each other, route signals along the shortest path, etc. For each harness, you can set its own set of properties, ensure its traceability in terms of time s x signal delays in it, copy routing plans between different projects. Allegro PCB Editor at the software level will “tell” the developer the optimal routes for laying the harnesses, and then, using unique algorithms, convert the resulting plan into a finished topology.

Accelerate time-dependent circuit design

The increasingly widespread use of high-speed digital interfaces, such as DDR3, DDR4, PCI Express, USB 3.0, imposes a number of restrictions that must be taken into account when designing a printed circuit board.

Allegro PCB Designer with High-Speed ​​option helps you quickly and efficiently meet the requirements of modern interfaces. This option expands the range of controllable electrical limits that the engineer can use to quickly achieve maximum signal integrity and ensure accurate timing. s e characteristics. Also, along with the High-Speed ​​option in Allegro PCB Designer, powerful tools for managing time-dependent circuits become available, such as Auto-interactive Delay Tuning, Auto-Interactive Phase Tuning, Auto-Interactive Convert Corner, Timing Vision, etc. Let's look at some of them in more detail.

The Auto-interactive Delay Tuning tool, abbreviated as AiDT, gives users the ability to quickly tune the length of a selected set of signals on the board, such as a byte path or an entire interface. This tool radically reduces the timing adjustment time s x delays for a large array of signals - from several hours to several minutes (Fig. 2). The user just needs to draw a selection frame around the desired set of signals, after which the length of the traces will be automatically adjusted in accordance with the parameters specified in the Constraint Manager.

The Auto-Interactive Phase Tuning tool, or AiPT, allows you to achieve optimal dynamic phase for a differential pair in minutes. The dynamic phase means ensuring the equality of the lengths of the conductors, taking into account their bends in different sections of the laying from the source to the signal receiver. Thanks to this tool, the time required to align the lengths of conductors in a differential pair is significantly reduced.

The user must continuously monitor the time-dependent circuits on the board. The specially developed Timing Vision visual inspection environment built into Allegro PCB Editor allows the user to quickly find inappropriate timings. s m trace restrictions on the printed circuit board. This tool includes color indicators, the ability to select a special pattern for routes, and special tooltips. Depending on the specified time s x restrictions in the Constraint Manager, the traces on the board will be highlighted in a different color, which is selected in the settings (Fig. 4).

Rice. 4. Timing Vision tool for visual control of the length of traces, taking into account the time dependence of signals

Design taking into account production technologies

Allegro PCB Editor supports Design for Testability (DFT), Design for Manufacturability (DFF), and Design for Manufacturability (DFA). All of these critical constraints are checked during the topology design phase, along with electrical constraints. Users can select the number of test points and their pad sizes, define exclusion zones for placing test points, and generate reports to verify the board's readiness for testing. Allegro PCB Editor includes a special function for monitoring DFA rules in real time. With its help, you can monitor and visually track any irregularities on the board related to the gaps between components. When components approach the maximum distance allowed by DfA rules, the program will automatically issue a warning and “stop” the user before a possible violation of the rules.

Data transfer to production

Allegro PCB Designer can generate a complete set of files for PCB production and testing, including Gerber 274x, NC Drill, NC Route, etc. But most importantly, Cadence supports the industry's move toward gerberless manufacturing technology with the new universal IPC-2581 format. The peculiarity of this format is that all the data necessary for the production, assembly, drilling, milling and testing of the board is stored in one unified file. Users can select data for the IPC-2581 file to protect their intellectual property. Importing IPC-2581 into Allegro PCB Editor allows you to view the file.

HDI board design route

Miniaturization is the main trend in electronics today. Devices are getting smaller while their performance and functionality are growing. Projects are increasingly using chips in BGA packages with pin pitches of 0.8 mm or less, which requires the use of high-density interconnect (HDI) technology to output signals to internal layers from BGA pads using fanouts. The design of the board in this case requires the use of microvias, placement of software on contact pads, and special manufacturing processes. All this must be taken into account in full by the PCB design system at the design rules control level.

Allegro PCB Designer in combination with the Miniaturization Option allows you to create projects based on HDI technology of any complexity. This includes the following features:

• working with micro holes;
• optimization of mixed vias;
• control of blind and blind holes on the layer;
• control of shelving of transition platforms;
• control of stepwise arrangement of transitions;
• a site within a site;
• mass production of transitions;
• control for compliance with manufacturing technology;
• taking into account HDI design rules during automatic routing.

Allegro PCB Designer, combined with the miniaturization option, includes many different interactive routing tools, such as blind and blind hole pushing, dynamic via mating, embedded component support, contour routing for rigid-flex boards, and more (Figure 5).

Embedded technology support

Reducing the size of the final product can be achieved in various ways. One of them is to place housing elements on the inner layers of the board. Allegro PCB Designer, with the miniaturization option, offers constraint-driven routing technology for embedded components. It supports both traditional direct and indirect connection technologies, as well as the latest bi-directional connection technologies for a single component, vertical component arrangement, and integrated components for a double-sided board. The miniaturization option allows the user to create and manipulate recesses on layers dedicated to housing embedded components.

Creation of analog RF and microwave boards

Allegro PCB Designer, coupled with Analog/RF Design, provides a mixed-signal design environment from schematic creation to historical planning to improve RF design productivity by up to 50%. This option allows engineers to create, combine and customize analog RF and microstrip circuits with digital and analog circuits in the Allegro PCB Designer environment. With advanced planning capabilities and powerful interfaces to RF simulation tools, this option gives engineers the ability to start the RF circuit design process from Allegro Design Authoring, Allegro PCB Designer or Agilent ADS.

Parallel team development

To reduce the duration of the development cycle, geographically dispersed development teams are increasingly being organized. Traditionally used in collaborative development, manual review and refinement procedures are very slow, time-consuming and associated with the risk of introducing errors.
Allegro PCB Design Partitioning technology implements a multi-user parallel design methodology to speed up the process and reduce planning time. With its help, many developers can work simultaneously, having access to a common database regardless of distance. Developers can divide the design process into a number of tasks or areas for which planning and editing will be done, and assign them to several team members. Developments can be divided vertically (sections) with software-defined boundaries or horizontally (layers). As a result, each designer can see all individual sections, observe the design process and evaluate the results of other designers. The ability to achieve this separation helps to significantly reduce development cycle times and speed up the design process.

Automatic PCB Routing Technology

PCB routing technologies are closely related to the PCB editor. Through the PCB Router interface, all design information and constraint conditions are automatically received from the PCB editor. At the end of the tracing, all information is automatically transferred back to the PCB editor.

Increased design complexity, density, and additional constraints for high-speed circuits make manual routing difficult and time-consuming. Solving the challenges of tracing complex connections requires powerful, automated technology. The robust and production-proven automatic router features a batch route mode with advanced route strategy control and built-in route strategies.

The Design For Manufacturing (DFM) tool included in the Allegro PCB Router significantly reduces the number of parts that are subsequently rejected. Its algorithms provide the ability to automatically space conductors using all available free space. Automatic conductor spacing helps improve manufacturability by moving conductors to further increase clearances between conductors and leads, between conductors and SMD pads, and freeing up additional space for conductive pads. Users take advantage of the flexibility to set tolerances either manually or by default.

Functions	Allegro PCB Designer
Allegro Design Authoring (Concept HDL) - entering information at the level of diagrams, tables and HDL descriptions
Allegro Design Entry CIS/Capture - schematic capture, centralized component database - CIS, access to the global Internet database of electronic components Active Parts
Constraint-Manager - physical, spatial and single chain rules
Constraint-Manager - changing individual properties of components and DRCs
Constraint-Manager - support for areas with local rules
Layout, placement, template placement Real-time DFA compliance
Supports IDF3.0, DXF in/out formats
New dynamic data exchange format with mechanical CAD systems - IDX (EDMD schema)
3D visualization of a printed circuit board
Hierarchical Interconnect Layout Route
Rules for controlling the length of conductors for high-speed signals
Constraint controlled route for high speed signals depending on wire length
Agreement groups, an individual set of rules for each layer, extended chains
Rules for T-connections (T-connection at pin)
Automatic meshless tracer (up to six layers)
Automatic routing based on high-speed rules
Automatic routing based on individual rules for each layer
Project planning - spatial topology planning based on feasibility and feedback	Design Planning Option
Project Planning - Topology Plan Generation	Design Planning Option
Project Planning - Converting Topology Plan to Alignments (CLINES)	Design Planning Option
Auto-interactive length construction for a selected group of signals	PCB High-Speed ​​Option
Constraint-Manager - electrical rules to account for signal reflection, timing and crosstalk	PCB High-Speed ​​Option
Electrical Rules Controlled Design Route	PCB High-Speed ​​Option
Electrical Rule Sets (ECSets)	PCB High-Speed ​​Option

Functions	Allegro PCB Designer
Mathematical description of design rules	PCB High-Speed ​​Option
Supports reverse drilling technology	PCB High-Speed ​​Option
Dynamic phase control, axis delays Z	PCB High-Speed ​​Option
Return path monitoring to ensure signal integrity	PCB High-Speed ​​Option
Constraint-Manager - a set of rules for HDI projects	Miniaturization Option
Pinholes and associative spatial, batch rules, including via-pad rules	Miniaturization Option
Constraint-driven development path for HDI projects	Miniaturization Option
Support of process rules for the production of boards with embedded components	Miniaturization Option
Support for rules for components embedded on the internal layers of the board	Miniaturization Option
Editing a Pinhole Stack in HDI projects	Miniaturization Option
Dynamic meshless mating, line extension, trace mating	Miniaturization Option
Tracing along a nonlinear contour (for flexible boards)	Miniaturization Option
Support of recesses (voids) on internal layers	Miniaturization Option
Parallel Engineering - Layering	PCB Team Design Option
Parallel engineering - distribution across functional blocks	PCB Team Design Option
Concurrent Engineering - Central status panel to manage the design process	PCB Team Design Option
Parallel Engineering - Chain Distribution	PCB Team Design Option
Editing restrictions between areas	PCB Team Design Option
Managing Net Classes Between Regions	PCB Team Design Option
Editing Parameterized RF Strip Elements	PCB Analog/RF Option
Asymmetrical gaps	PCB Analog/RF Option
Two-way interface with Agilent ADS	PCB Analog/RF Option
Importing Schematics from Agilent ADS into Design Entry Authoring	PCB Analog/RF Option
Design of microwave boards	PCB Analog/RF Option
Built-in polygon editor for microwave topology	PCB Analog/RF Option
Automatic routing up to 256 layers	PCB Routing Option
Automatic routing based on DFM rules	PCB Routing Option
Automatic route distribution	PCB Routing Option
Automatic generation of control points	PCB Routing Option
Tracing based on individual rules for each layer	PCB Routing Option

During routing, free corners and control points can be specified. DFM algorithms automatically make optimal indents, starting with the largest ones and reducing them within accessible limits. The test point creator automatically inserts test vias or pads on the board. Test points in the form of test vias can be located on both the front and back sides of the board, allowing the use of single-sided or double-sided testers. Developers have the option of selecting a checkpoint insertion methodology that suits their production requirements. Test points can be fixed to avoid the need to modify the test fixture. Constraints for test points include the surface shape of the test probes, via sizes, meshes, and minimum hole center distances.

Automatic constraint-driven routing for high-speed boards

High-speed constraint conditions and routing algorithms apply differential pairs, network planning, timing s e signal parameters, crosstalk levels, layer stack routing, and special geometry requirements for today's high-speed circuits. Automatic routing algorithms accurately route into and around vias and automatically maintain compliance with specified timings. s m or spatial criteria. Automatic network scheduling is used to reduce noise levels in noise-sensitive circuits. You can apply different design rules to different areas of the board, for example, you can set a rule for maximum density in the area of ​​\u200b\u200bthe conductors and less strict rules for the rest of the board.

The development of high-speed electronics must be supported by adequate software and hardware design tools. Allegro PCB Designer is a powerful tool in the hands of a professional designing modern, high-speed electronics. The latest update, Update Release No. 2, released in March of this year, includes a large number of new work tools, which were partially described in this article.

To develop electronics you need at least knowledge of circuit design, knowledge of a modern electronic component base, the ability to work in one of the CAD programs and lay out boards in accordance with EMC requirements. And if you have not yet decided which CAD software you will mainly work with, then this article is for you.

There are currently three professional CAD environments for electronics: Altium Designer, Allegro Cadence and Mentor Graphics PADS. Any semi-professional ones like Proteus, Eagle, etc. are not even worth considering, since they are at the amateur radio level and do not allow you to do any complex things. There are also various archaic, specialized ones, such as Microwave, Uniboard and others, but they are also not worth considering due to their low popularity and as a result of the lack of support.

In this article I want to give an overview and talk a little about how to work in Allegro Cadence, since I myself use this environment for the following reasons:

• First of all, Cadence's capabilities are quite impressive. It would take only a separate article to list everything, but I’ll talk about some of it below.
• Secondly, Cadence is not very demanding on the system; it will work fine even on very weak computers like 1 GHz, 512 RAM. If your computer does not have 2 cores, then you actually have no other choice other than Cadence, because... When developing, I often, if not always, have to keep several software packages open at the same time, in my case SolidWorks and Cadence; if I had launched, for example, Altium, my computer would simply go up in smoke.
• Thirdly, there are no such glitches as in Altium (I don’t know about Pads). Of course, there are some inconvenient things in Cadence, I must say here they have their own shell, completely built on scripts and controlled from the command line, this may seem inconvenient to many, but there are no such critical errors as, for example, occur in Altium when converting files to gerber and generally a fairly stable environment in this regard.

So, what is Allegro Cadence? This is a package of programs and utilities that are well connected with each other. Each program is responsible for its own area and is launched separately. There are quite a lot of them out there, and a story about any of them would require a separate article, so I will list and briefly talk only about those that an ordinary electronics engineer needs, just to know what to start working with.

Design Entry CIS
This program is for designing a circuit diagram, simulating it, drawing diagrams, etc. Those. here you create or insert components, bind footprints to them, specify rules that will be checked at the end to eliminate errors, rooms, etc. In general, Design Entry CIS can contain your entire project, including documentation, but for starters this is all unnecessary information, so I’ll briefly tell you what and how to do.

File->New->Project
Everything was created. Go to the circuit diagram page PAGE1 and click Place Part, then Add Library and select the necessary libraries. You can create your own component libraries and even need to add them to the project.

Drawing

Ok, let's add a library of discrete elements Discrete and MicroController. Let's say we want to make a circuit containing a pair of resistors, capacitors and an STM32 microcontroller. To do this, select the Discrete library and look for “CAP POL” and “RESISTOR” in the Part List above, i.e. polar capacitor and resistor. We insert them into the circuit and then look for STM32 microcontrollers in the MicroController library. But bad luck, they are not there. What do we do? Create a case from scratch?

No, there is an easier option, right-click on an empty spot in the diagram and select Place Database Part from the menu and in the tab that opens click on Internet Component Assistant

Drawing

In the built-in browser window, click on Active Parts with the OS icon. Next, in the window that opens, we see a bunch of settings, but we don’t touch anything, but enter the Part Number: “STM32” into the line.

Drawing

Next, we select the controller we need or one close to it (so that we can finish it a little), indicate which library to insert into, indicate if there is a footprint, etc. If you don’t know what to indicate, then click on Place Part constantly.

To link a footprint to a component, you need to go to its properties, double-click on the component and find the corresponding column. The name of the footprint is the name of its file, and the footprints themselves are located in the directory ..\Cadence\SPB_16.5\share\pcb\pcb_lib\symbols you can’t change this, and if you find it somewhere, then it’s better not to, Cadence really doesn’t like it when something is pointed out to him wrong. On the other hand, if he doesn’t like something, he will definitely tell you.

I would like to immediately tell you about the files that are in the ..\symbols folder.
*.dra - files of our components, in other words our footprint
*.bsm - mechanical holes
*.pad - pad files
*.psm - padstack files, in general should be in the same place as *.dra

In order to make a board, you need to know one more thing, this is how to make a netlist so that you can route the board. To do this, you need to go to the project page, select it and click on Create netlist, there are 1500 settings, but I believe that you will figure it out. And don't worry, if Cadence is unhappy with something, it won't let you mess up the circuit and will send you an error, which it does often. Be sure that you will still love him, even if you hate him at first. C'est la vie.

Package Designer
If you get an error when creating a netlist Cadence, then most likely you are missing a footprint somewhere. There are two ways to fix this, the first is to exclude the component from the physical model, and the second is to add it, and if not, then create a footprint component. For this we need the Package Designer program. This is the same environment as in the PCB Editor board design program, so almost everything here is the same, both controls and many functions.

It opens files of the *.dra type, so to avoid too much trouble, go to the symbols directory in the ..\pcb_lib\symbols folder and open some file with the *.dra extension. A component consisting of a bunch of layers will appear in front of you. Now a little about how to live in this space in general, because... if you try to call and do something sane, you will be surprised how inconvenient everything is here, but this is at first glance... in general, on the second and third too, as I already said, you will still hate Cadence, but it’s okay then you will come to terms with it and you’ll even love him so much that you won’t say goodbye, it’s forever. Seriously.

Drawing

So, the controls here are a little unusual. By holding down the middle mouse button you can move the window; to zoom you need to turn the mouse wheel. Everything here is done something like this: click on the object -> right mouse button -> command -> execute. You need to practice, it’s not immediately clear how and why, you’ll understand later. Much is done from the command line, this is a separate discussion.

On the right we see the control panel, which consists of three tabs: Options, Visiability, Find

Drawing

Options- it lists the classes of layers with which we will work; it is necessary to know only a few.
Find- here we note which specific elements we will work with, and if it’s easier, which ones we will choose. Let's say if I want to select only pins and not touch the pipes, then I need to check the Pins box.
Visiability- here we mark which elements will be visible to us and which are hidden so as not to interfere. Not all layers are there, but only the main ones.

You can master everything on the panel yourself, I’ll tell you only the main things here.

Menu Display->Color/Visiability- here you configure the colors of the elements and their visibility on the diagram.
Menu Setup->Design Parameters- an important menu that configures the project. Grids - a grid with which steps you will move elements. Text - default text setting.
Menu Setup->Areas->Part Height- a very important option if you want to transfer the board to a 3D model, it sets the height of the component by snapping it to the Place_Bound_Top / Bottom layer.
Menu Shape- Form management here. Shapes are anything, from a polygon to a component body.
Menu Layout->Pins- insertion of pins.

In general, that’s all for this program, I repeat that it’s the same as in PCB Editor, many of the options are even the same. But we’ll look at it later, because... To create a component, you need to be able to create your own pads, and for this we need the following utility.

Pad Designer
As you may have guessed, this utility creates the pads that you need in order to assign them to components in Package Designer. There are a lot of settings here and it’s hard to find what’s not here, from an arbitrary pad shape to drilling holes using plasma or laser, in general, all this is important for production. First, open some *.pad in the ..\symbols folder, so you can see how and what to enter.

PCB Editor
And finally we moved on to the most important program. It allows you to arrange your components and wire them according to the electrical diagram. It’s the same as in Package Designer, only even more. There is no point in talking about this program in detail, because... You could write a dozen articles about it alone, there are a lot of tricks, subtleties, pitfalls, etc. I will list only the important menus so that you don’t have to search when learning.

Manufacture menu- here is everything regarding preparation for board production. Conversion to gerberas, drill legend, layer diagram, etc.
Cross section (Xsection)- physical layers are assigned there. Their number, thickness, material, order. This can be obtained from the board manufacturer.
Constraint Manager- this is a whole subroutine, it sets the rules for routing and clearing, you can, for example, make sure that one of the nets is not shown in rats.

In general, the rest can be more or less figured out through trial and error. Just for clarity and as an example, I’ll show a piece of a wired board:

In general, that’s all, this was a short overview, just to understand how and what works here, of course, for this it’s not enough to just read the articles and you need to install Cadence and make a board to understand what the ideology is here. This is not just an ordinary program for Windows; if you get hooked on it, you won’t get off it. Perhaps at first a lot of things will seem inconvenient to you, but after understanding the details you will understand that everything is even right.

And three more points. When laying out the board, when you work with polygons, you need to enter this command set etchedit_ignore_dynamic_shapes otherwise it will be impossible to draw anything, the polygons will interfere with the paths and you will die dragging them. Does it surprise you that without one command, which is not registered anywhere, it is impossible to install a normal board? Well, everything is like this, this is Cadence, at first you will despise those sadists who made it, but then everything will change and you will no longer need another CAD system except Cadence.

The second point is this. It is not necessary to create footprints manually, because... there are many programs that generate them for you. The most famous are LP_Wizard and PCB Library Editor, they are paid. But there is another one, and in my opinion it’s very good and seems to be a free Footprint maker, you can download it

Cadence AllegroPCB Design Solution- a scalable, proven PCB development environment designed to solve modern technological and methodological problems, to reduce and increase predictability of development cycles.

Description

Allegro PCB Design Solution comes standard with a variety of options and contains everything you need to create PCB layers in a fully integrated design flow. The Allegro PCBDesigner environment contains everything you need to design simple and complex printed circuit boards

Fig. 1 - The Allegro PCB Designer environment contains everything you need to design simple and complex printed circuit boards

The basic Allegro PCB Designer package includes: a common module, a constraint management environment, a printed circuit board editor, an automatic or interactive router, tools for saving data in industrial formats, and a mechanical design environment for structural components (CAD).

The PCB Editor provides a comprehensive environment from basic planning, placement and routing to replication and advanced planning with intermediate elements for simple and complex PCB designs (Figure 1).

Advantages

• Is a proven, scalable and cost-effective PCB editing and routing tool, available as standard and with a range of configuration options
• Eliminates unnecessary iterations with constraint-driven design flow
• Supports an extensive set of rules for specifying physical sizing, spacing, process, installation and testing (DFx), high-speed interconnect (HDI), and electrical high-speed domains
• Has a general constraint condition management system to create, control and check these conditions from end to end
• Allows interoperability with third-party packages to speed up the design process and leverage the best in integrated development tools

PCB Editor technology

Constraint-Based PCB Editing Environment The main component of Allegro PCB Designer is the PCBEditor layout editor, an intuitive and easy-to-use environment for creating and editing both simple and complex PCB designs that are subject to constraint conditions. DFA (Design For Assembly) placement technology allows components to be placed compactly and accurately

Fig. 2 – Placement technology guided by DFA (Design For Assembly) installation rules allows for compact and error-free placement of components

A wide range of functions meets numerous design and production requirements:

• Powerful set of planning and placement tools, incl. replication to speed up the development process
• Interactive tools for moving, compressing and editing areas create a high-performance real-time interaction environment with display of geometric and temporal boundaries
• Dynamic shapers have functionality for cutting and merging copper polygons during motion and routing iterations
• PCB Editor can also generate a full suite of photomasks, test outputs including Gerber 274x, NC drill and bare-metal PCB inspection tests in a variety of formats.

Managing Constraints

The constraint management system displays real-time geometric dimensions, spacing, high-speed data with compliance status for each development stage. Each worksheet provides an interface for creating, managing, and testing various rules in a hierarchical manner. Using this powerful application, designers can create, edit and view sets of constraint conditions in the form of graphical topologies that act as electronic “light copies” of the ideal implementation strategy. Because constraint conditions are associated with a database, they can guide the placement and routing processes for given signals.

The constraint control system is fully integrated into the PCB Editor and verification can be carried out in real time during the design process. The test results are displayed graphically: areas that successfully passed the test are highlighted in green, and areas that do not meet the limiting conditions are highlighted in red. This allows designers to directly observe the design process and see the effect of any design changes.

Planning and placement

The constraint-driven PCB design methodology includes a flexible and powerful set of automatic and interactive placement tools. An engineer or designer may place components or circuits in special "rooms" during design or planning. Components can be filtered or selected by special designation, chassis or footprint type, network name (title), component number, or table or schematic page number.

This control precision is necessary in modern circuits containing thousands of components. Real-time assembly analysis and feedback helps improve this control, increasing productivity and efficiency by placing components in accordance with corporate rules or recommendations based on electromagnetic simulation results.

Dynamic placement, guided by design-for-assembly rules (DFA), allows each package to be verified during interactive component placement (Figure 2). Feedback generated from a two-dimensional matrix of body classes and prototypes ensures minimum tolerance requirements. Using side-to-side, back-to-back principles, designers can place components to simultaneously achieve optimal routing, manufacturability, and signal properties.

Copying placements

Allegro PCB Designer's superior layout copying technology allows users to quickly place and route similar circuit sections. It allows you to create a circuit and routing template that can be applied to all similar sections of the circuit. The component placement pattern can also be used in other designs with similar circuits. When copying placements, it is possible to rotate or mirror the copied object horizontally or vertically. All elements associated with an object, including hidden blind vias, appear in the correct layers when the object is flipped.

Display and Visualization

All PCB Editor software packages have a built-in 3D visualization tool. The 3D interface supports various filtering options, simulated camera viewing, graphical display options such as solid, transparency and wireframe, and mouse-controlled display panning, zooming and rotating. 3D mode also supports display of complex through-hole structures and isolated sections of the board. Using the contextual control structure, many windows can be opened, and 3D images can be copied and saved in JPEG format (Figure 3).

The ability to flip the board ("flip") allows you to flip the board along the Y axis, accordingly inverting the database at the boundaries. This operation reorganizes the display of the structure so that the top of the structure is at the bottom and the bottom is at the top. It is very important for CAD systems to be able to display bottom views for engineers involved in laboratory debugging of boards or testing during production. The ability to flip the board over isn't just for viewing; it also allows you to make changes to its design. Built-in 3D rendering allows you to view board sections or complex via structures from multiple angles, magnifications, rotations, and rotations to reduce iterations for mechanical designers and PCB manufacturers and prevent the introduction of errors.

Rice. 3 – Built-in 3D rendering allows you to view board sections or complex via structures from multiple angles, magnifications, rotations, and rotations to reduce iterations for mechanical designers and PCB manufacturers and prevent the introduction of errors.

Interactive editing

The PCB Editor Routing Option provides powerful, interactive tools to control the automatic routing process and improve its performance. Working with any shape, angle, or relative movement of components, routing tools allow users to choose different priorities for actions.

During editing, the developer can see in real time how much time remains to complete connections within the specified tight time constraints. The interactive mode also allows for group tracing of many networks and interactive configuration of networks of long length and with restrictions on acceptable delays.

Tire tracing

Bus routing mode (Multi-Line Routing) is designed for routing a large number of lines on a printed circuit board at once. Combined with the “contour capture” option, this utility allows you to trace many lines in a structure containing both flexible and rigid elements in a matter of minutes, while routing individual lines would take hours. The “contour capture” option is responsible for inserting lines into the flexible part of the structure (Fig. 4).

Bus routing with contour capture option speeds up the routing process on flexible areas of PCB designs

Rice. 4 – Bus routing with edge capture option speeds up the routing process on flexible areas of PCB designs

Planning and Routing

Planning and routing high-density PCBs with many constraints and bus connections can take a significant amount of time. Complicating the process is the miniaturization of modern components, new electrical signal levels, and special layout requirements, so it is not surprising that traditional CAD technologies and tools cannot fully realize the designer's intent. Global Route Environment provides the technology to take the designer's intent and stick to it. Thanks to its connection planning architecture and global routing process, for the first time, users can bring their experiences and ideas to life in a tool that understands them naturally.

Users create abstracted link data using a link path planning architecture, quickly convert it into a complete solution, and can validate that solution using a global routing program. The use of connection abstraction makes it possible to reduce the number of elements from tens of thousands to hundreds, which leads to a significant reduction in the amount of direct manual work of the designer.

When using abstract data, the planning and routing process can also be accelerated by applying a spatial visualization of the open area along with the data and the designer's intent. The routing program then works out all the connection details according to that design, without requiring the assistance of the user, who previously had to simultaneously control the routing process and resolve connection problems. The resulting significant simplification of the development process compared to current tools allows users to create effective solutions faster and easier, reducing development cycle times and increasing productivity (Figure 5).

Allegro Interconnect Flow Planner technology allows users to reduce the number of layers and significantly reduce development cycle times

Rice. 5 – Allegro Interconnect Flow Planner allows users to reduce the number of layers and significantly reduce development cycle times

Designing High-Speed ​​Boards

The increasingly widespread use of the latest standard interfaces, such as DDR3, DDR4, PCI Express, USB 3.0, imposes a number of restrictions that must be taken into account when designing a printed circuit board.

Allegro PCB Designer with High-Speed ​​option helps you quickly and easily meet the demands of modern interfaces. This option extends the set of controlled electrical constraints that ensure that the PCB design meets the specifications of modern interfaces.

In addition, High-Speed ​​allows users to enter advanced design rules by using formulas in conjunction with existing rules or resulting data, such as actual wire lengths.

Accelerate time-dependent circuit design

Allegro PCB Editor with High-Speed ​​option significantly speeds up work on high-speed interfaces using the new Auto-interactive Delay Tuning (AiDT) tool. AiDT allows users to quickly adjust the length of a selected set of signals on the board, for example, a byte path or the entire interface. This tool radically reduces development time - from several hours to several minutes (Fig. 6).

Rice. 6 – Automatic adjustment of wire lengths before and after using the new Auto-interactive Delay Tuning tool

Supports reverse drilling technology

Design taking into account production technologies

Allegro PCB Editor supports design-for-test (DfT), design-for-manufacturability (DfF), and design-for-assembly (DfA). All of these critical constraints are checked during the topology design phase, along with electrical constraints. Users can select the number of test points and their pad sizes, define exclusion zones for placing test points, and generate reports to verify the board's readiness for testing. Allegro PCB Editor includes a special function for monitoring DfA rules in real time. With its help, you can monitor and visually track any irregularities on the board related to the gaps between components. When components come close to the maximum distance allowed by DfA rules, the program will automatically issue a warning and “stop” the user before a possible violation of the rules.

Data transfer to production

Allegro PCB Designer can generate a complete set of files for PCB production and testing, including Gerber 274x, NC Drill, NC Route, etc. But most importantly, Cadence supports the industry trend towards "gerberless" manufacturing technology with a new universal IPC-2581 format. The peculiarity of this format is that all data necessary for production, assembly, drilling, milling and testing of the board is stored in one unified file. Users can select data for the IPC-2581 file to protect their intellectual property. Importing IPC-2581 into Allegro PCB Editor allows you to view the file.

Miniaturization

Constraint Driven HDI Design Path

When using BGA packages with pin widths of 1.0-0.8 mm or less, down to 0.5 mm, users must use high-density interconnect (HDI) technology. Although miniaturization is not a primary goal for many market segments, the use of BGAs requires a stacking transition is inevitable when routing complex BGA packages with three or more rows of pins on each side.

Allegro PCB Design, coupled with the Miniaturization Option, provides an end-to-end design path with control of a full set of rules and constraints for a variety of HDI design styles, from hybrid stack/stack to fully process-based stacking, such as ALIVH.

In addition, Allegro PCB Editor includes automatic tools for applying HDI technology to projects to reduce development time and consistently improve designs (iterative design method) (Fig. 7).

Rice. 7 – Dynamic pairing of pads and conductors during interactive routing significantly saves time at the stage of preparing the project for production

Embedded technology support

Reducing the size of the final product can be achieved in various ways. One of them is to place housing elements on the inner layers of the board. Allegro PCB Designer, with the miniaturization option, offers constraint-driven routing technology for embedded components.

It supports both traditional direct and indirect connection technologies, as well as the latest bi-directional connection technologies for a single component, vertical component arrangement, and integrated components for a double-sided board. The miniaturization option allows the user to create and manipulate recesses on layers dedicated to housing embedded components.

Creation of analog RF and microwave boards

Allegro PCB Designer, coupled with Analog/RF Design, provides a mixed-signal design environment from schematic design to historical design to improve RF design productivity by up to 50%. This option allows engineers to create, combine and customize analog RF and microstrip circuits with digital and analog circuits in the Allegro PCB Designer environment. With advanced planning capabilities and powerful interfaces to RF simulation tools, this option allows engineers to begin the RF circuit design process from Allegro Design Authoring, Allegro PCB Designer or Agilent ADS.

Parallel team development

To reduce the duration of the development cycle, geographically dispersed development teams are increasingly being organized. Traditionally used in collaborative development, manual review and refinement procedures are very slow, time-consuming and associated with the risk of introducing errors.

Allegro PCB Design Partitioning technology implements a multi-user parallel design methodology to speed up the process and reduce planning time. With its help, many developers can work simultaneously, having access to a common database regardless of distance. Developers can divide the design process into a number of tasks or areas for which planning and editing will be done, and assign them to several team members. Developments can be divided vertically (sections) with software-defined boundaries or horizontally (layers). As a result, each designer can see all individual sections and see the design process and the results of other designers. The ability to achieve this separation helps to significantly reduce development cycle times and speed up the design process.

Automatic PCB Routing Technology

The Allegro PCB Router's Design For Manufacturing (DFM) tool significantly reduces the number of parts that are subsequently rejected. Its algorithms provide the ability to automatically space conductors using all available free space. Automatic conductor spacing helps improve manufacturability by moving conductors to further increase clearances between conductors and leads, between conductors and SMD pads, and freeing up additional space for conductive pads. Users take advantage of the flexibility to set tolerances either manually or by default.

During routing, free corners and control points can be specified. DFM algorithms automatically make optimal indents, starting with the largest ones and reducing them within accessible limits. The test point creator automatically inserts test vias or pads on the board. Test points in the form of test vias can be located on either the front or back side of the board, allowing the use of single-sided or double-sided testers. Developers have the option of selecting a checkpoint insertion methodology that suits their production requirements. Test points can be fixed to avoid the need to modify the test fixture. Constraints for test points include the surface shape of the test probes, via sizes, grids, and minimum hole center distances.

Automatic constraint-driven routing for high-speed boards

High-speed constraints and routing algorithms use differential pairs, network scheduling, signal timing, crosstalk levels, layer stack routing, and the special geometry requirements of today's high-speed circuits. Automatic routing algorithms accurately route into and around vias and automatically maintain compliance with specified timing or spatial criteria. Automatic network scheduling is used to reduce noise levels in noise-sensitive networks. Separate design rules can be applied to different areas, for example, you can set a rule for maximum density in the area of ​​​​the conductors and less strict rules for the rest of the board.

• added a fully functional ability to load 3D models of components and mechanical parts in STEP format for visual inspection of gaps. A STEP model can be added directly in the symbol editor or topology editor. The special variable steppath specifies the path to the STEP model libraries on the user's local disk or server. The finished topology can now be exported in STEP format to mechanical CAD systems. At the same time, various export options are supported to control the size of the overall STEP board model;

• Added new Auto-Interactive Breakout (AiBT) technology. Its essence lies in the fact that the program, depending on user actions, automatically creates conductors at both ends of the bus or interface. In this case, the circuit lines on the board must be combined into a common bundle. When tracing, a mode is supported where the user can see both ends of the link simultaneously on one screen;

• Added new Auto-Interactive Add Connect (AiCC) tracing tool. This command works in two modes - manual and automatic. Manual mode is no different from the standard Add Connect command. When starting the automatic mode, the user first draws a curved line along the route, and then this curve is converted into a finished route;

• The new Detune command allows you to delete the result of adjusting a single trace or several traces along the length. This function is very convenient if you need to move routes or change delay restrictions.

The beginning of 2003 was marked by the release of a number of new versions of popular printed circuit board design systems. Some of them have undergone minor changes, some have been completely updated, but all of them, without exception, have increased their capabilities. The cost of EDA products greatly depends on their functionality, so below we will try to show users the main details that should be kept in mind when choosing a design system.

Any PCB design system is a complex set of programs that provide an end-to-end cycle, starting with drawing a circuit diagram and ending with the generation of control files for equipment for the production of photo masks, drilling holes, assembly and electrical control. However, modern market conditions impose additional requirements on these systems.

The best results were achieved by Mentor Graphics (www.mentor.com/pcb). With its own Mentor BoardStation PCB design system, the company absorbed two of its competitors, Verybest and Innoveda, and now continues to develop the Expedition PCB and PADS PowerPCB product lines. The key to the company's success was its focus on modern integrated design environments for Windows.

Expedition PCB provides the most powerful board design solution available today. The system is based on the AutoActive environment, which allows the implementation of functions such as pre-topological analysis of signal integrity, interactive and automatic routing, taking into account the requirements of high-frequency boards and special technological limitations imposed by the use of modern element base (BGA). A unified environment allows, using the ICX module, to simulate interference in conductors directly when laying a route or bus and control whether they exceed a given level (Fig. 1). This product has only one drawback - its high cost, which is an important obstacle to penetration into the Russian market.

Figure 1. Analysis of interference in adjacent conductors when laying a route in the Expedition PCB package

Another Mentor product, the PADS PowerPCB system (www.pads.com), offers a lower-cost solution. This system boasts the best BlaseRouter autorouter, which supports all the functions necessary for routing high-frequency boards (Fig. 2). The package has pre-topological (HyperLinks LineSim) and post-topological (HyperLinks BoardSim) analysis modules that closely interact with the constraint control system. These modules have now been significantly improved by incorporating original modeling algorithms previously used in Innoveda's XTK product.

Figure 2. Automatically reshape the conductor with controlled length when moving a capacitor in a PADS PowerPCB package

Next in terms of the power of the solutions offered is Cadence. For the top level of design, the PCB Design Studio package is available (www.pcb.cadence.com). The Allegro program is used as a PCB editor, which allows you to develop multi-layer and high-speed boards with high component density. The SPECCTRA program (www.specctra.com) is used here as a standard auto-placement and auto-routing module, controlled by an extensive set of design rules and technological constraints. Electromagnetic compatibility analysis of the board topology is performed using a special SPECCTRAQuest SI Expert module; the SigXplorer module is used for preliminary design analysis and preparation of sets of design rules.

Another Cadence product, OrCAD (www.orcad.com), is recommended as a lighter, cheaper solution for PCB design. Recently, the product has hardly been developed, as indirectly evidenced by the latest version numbers (9.1, 9.2, 9.22, 9.23). This package is considered by Cadence as a priority system for design input and modeling: Capture CIS and PSpice modules are now supplied as part of the PCB Design Studio package. The latest version of OrCAD includes new NC Sim digital logic circuit synthesis and simulation capabilities. The OrCAD Layout PCB Editor has three different configurations with different functionality. A board design can contain up to 30 layers, 16 of which can be signal layers. There are built-in auto-placement and auto-routing tools, as well as an interface with the SPECCTRA program.

The third manufacturer of CAD printed circuit boards is the Australian company Altium (www.altium.com). Thanks to a skillful investment policy, this company was able to minimize losses associated with the decline of the high-tech market in 2002. In August 2002, the company released Protel DXP (www.protel.com), a continuation of Protel's own original product lines. This package provides an end-to-end design cycle for mixed analog-to-digital printed circuit boards using programmable logic from Xilinx and Altera. All tools are implemented on the basis of the integrated design environment Design Explorer, running under the Windows XP operating system. To the previously available means of post-topological analysis of signal integrity (Signal Integrity), the ability to perform pre-topological analysis has been added. But the main innovation of the Protel DXP system was to be the topological autorouter Situs, designed to implement a new approach to automatic board routing.

With the Protel DXP development effort fully underway, Altium continues to develop its second PCB design package, P-CAD 2002 (www.pcad.com). This system remains quite popular in Russia, which is rather determined by the attachment of our developers to the name P-CAD (at one time Altium made a skillful marketing move by renaming the ACCEL EDA package to P-CAD). The latest version of P-CAD 2002 was released in December 2002, but it does not contain any fundamental innovations, and the existing ones would be enough for the next Service Pack. The main changes affected the user interface, which became more Protel-like. The only thing that the P-CAD 2002 system can boast of is high-quality support for the ODB++ output data format.

It is impossible not to mention another product, almost unknown in Russia, but quite powerful and popular in the world - Visula from Zuken (www.zuken.com). The company's products support the end-to-end design cycle and offer powerful tools for modeling and synthesizing programmable logic followed by PCB design. It has a standard set of tools, as well as its own auto-placement and auto-routing tools. It should be noted that Zuken also offers users integrated 3D solid modeling tools for the devices being developed (Fig. 3).

Figure 3. Three-dimensional board modeling using Zuken

It is easy to see that the power of all the programs listed above is largely determined by the built-in electromagnetic compatibility analysis tools. In this regard, it is worth noting some specialized programs. Modern trends in the development of digital technology dictate the need to change the approach to this problem. Most modern EMC analysis programs use microstrip line models that assume the power and ground conductors are ideal, and do not take into account the current distribution in them.

A pioneer in this area was Sigrity (www.sigrity.com), which developed the Speed ​​XP package. This program does not use simplified models, but numerical methods for solving electrodynamic problems, which makes it possible to study the propagation of interference along the internal power layers (Fig. 4). However, the presence of such powerful mathematics makes the program almost an order of magnitude more expensive than the products of its closest competitors, who are attempting to implement similar methods in their systems, such as Mentor Graphics.

Figure 4. Sigrity Speed ​​2000 Ground Plane Noise Analysis

Of the programs that implement the classical approach to EMC analysis, we should note the company Quantic EMC (www.quantic-emc.com), which offers the Omega PLUS product to the market. In addition to the usual analysis of signal integrity and crosstalk distortion, the emission spectra of the board in a given frequency range, the current levels in the conductors, as well as the intensity of the electric and magnetic fields above the board can be obtained.

A separate task in PCB design is thermal analysis. The most powerful solution in this area is the BETA Soft-Board program from Dynamic Soft Analysis (www.betasoft-thermal.com). There are also interfaces for importing projects from all of the above products, rich libraries of models and materials. During the calculation process, temperatures of individual components, board heating maps, and temperature gradients can be obtained (Fig. 5). Note that the BETASoft-Board program is supplied as a standard thermal modeling tool for Mentor Graphics products.

Figure 5. Thermal analysis of the board in the BETASoft-Board package

Another thermal analysis program, Sauna, from Thermal Solutions (www.sauna.com), allows you to simulate the behavior of not only boards, but also blocks and cabinets. There are extensive libraries of components and materials. There is a special graphic editor that allows you to draw the equipment configuration. The system makes it possible to assign special operating cycles taking into account the switching on and off of external power sources.

A set of utilities and programs that allow you to design integrated circuits, conduct analog and digital modeling, develop and prepare high-level multilayer printed circuit boards for production.

Along with Mentor Graphics PADS, Allegro Cadence is the most advanced and user-friendly electronics design system in the modern world. The Allegro Cadence environment has its own unique shell, almost entirely built on scripts and controlled from the command line. Many developers find it inconvenient, however, it is a recognized leader in stability, absence of “bugs” and critical errors.

The basis of the Allegro Cadence package is the basic PCB Design Studio set, consisting of three modules that contain all the necessary tools for end-to-end board design:
1. Concept HDL or Orcad Capture CIS to choose from. Two schematic editors with built-in element management tools, each with its own approaches and strengths. The simpler Orcad Capture CIS is ideal for quickly working on a project with Internet access to the widest component base. Concept HDL is suitable for teams developing complex projects. All work can be easily divided into manageable single-task modules and distributed among designers.
2. Allegro PCB – an interactive shell for creating and editing printed circuit boards of any complexity with the capabilities of topology planning, routing and preparation for production.
3. SPECCTRA - a program consisting of a trace editor and an autorouter. Both tools integrate with Allegro PCB.
In addition, the package contains the PE Librarian utility, designed for creating and managing element libraries.
The standard modules of the Allegro Cadence basic set are upgradeable. This allows you to increase some of their characteristics, and also provides access to additional functions in accordance with the latest production requirements. For example, improvements are available:
Allegro performance option – expands the sets of rules for the development of high-speed printed circuit boards;
SPECCTRA upgrade – increases the number of layers during auto-routing to 256;
PSpice A/D – allows you to perform analog and mixed modeling;
SPECCTRA Quest – performs qualitative research of signals before and after topology tracing.

Powerful synchronization tools automatically propagate changes made in the main part of the project to all its versions. You can determine the desired version at any stage of development: when creating a list of consumables, during modeling, or when generating data for production. This can be done both from the topology editor and from the circuit input.

The annual cost of the basic Allegro Cadence set is approximately 4,000 US dollars. In addition, there is also an extended basic, advanced and maximum version of the design environment under consideration. The high price is the main disadvantage of this package, limiting its use. Not only individual radio amateurs, but even large companies specializing in the development of printed circuit boards and interested in efficiency and productivity cannot always afford to purchase the program. From this page you can download trial versions of a number of modules of the software package.

The utilities included in Allegro Cadence were developed by programmers from Cadence Design Systems (http://www.cadence.com/), which also has all rights to OrCAD. In addition to developing popular integrated circuit design packages (Virtuoso, Encounter, Incisive Platform) and printed circuit boards (Allegro and OrCAD), the company provides the ability to test third-party software on virtual chips before the microprocessors themselves are released.
Currently, the central office of Cadence Design Systems is located in the USA, in the city of San Jose, the majority of employees work in Silicon Valley, and more than sixty branches of the company have already been opened around the world.

The interface language of the Allegro Cadence software package is English only.